74LVQ138低压1-of-8解码器/多路解复用器
February 1992
Revised June 2001
74LVQ138
低电压1-of-8解码器/多路解复用器
一般描述
The LVQ138 is a high-speed 1-of-8 decoder/demultiplexer.
This device is ideally suited for high-speed bipolar memory
chip select address decoding. The multiple input enables
allow parallel expansion to a 1-of-24 decoder using just
three LVQ138 devices or a 1-of-32 decoder using four
LVQ138 devices and one inverter.
特点
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Improved latch-up immunity
s
Guaranteed incident wave switching into 75
Ω
s
4kV minimum ESD immunity
s
Demultiplexing capability
s
Multiple input enable for each expansion
s
Active LOW mutually exclusive outputs
订货代码：
Order Number
74LVQ138SC
74LVQ138SJ
Package Number
M16A
M16D
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
逻辑符号
连接图
IEEE/IEC
引脚说明
Pin Names
A
0
–A
2
E
1
–E
2
E
3
O
0
–O
7
Description
Address Inputs
Enable Inputs
Enable Input
Outputs
© 2001 Fairchild Semiconductor Corporation
DS011350
www.fairchildsemi.com
