100331低功耗三D触发器
August 1998
100331
低功耗三D触发器
一般描述
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CP
C
), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CP
n
), Direct
Set (SD
n
) and Direct Clear (CD
n
) inputs. Data enters a mas-
ter when both CP
n
and CP
C
are LOW and transfers to a
slave when CP
n
or CP
C
(or both) go HIGH. The Master Set,
Master Reset and individual CD
n
and SD
n
inputs override
the Clock inputs. All inputs have 50 kΩ pull-down resistors.
特点
n
n
n
n
n
n
35% power reduction of the 100131
2000V ESD protection
Pin/function compatible with 100131
Voltage compensated operating range = −4.2V to −5.7V
Available to industrial grade temperature range
Available to Standard Microcircuit Drawing (SMD)
5962-9153601
逻辑符号
Pin Names
CP
0
–CP
2
CP
C
D
0
–D
2
CD
0
–CD
2
SD
n
MR
MS
Q
0
-Q
2
Q
0
–Q
2
DS100300-1
Description
Individual Clock Inputs
Common Clock Input
Data Inputs
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
Data Outputs
Complementary Data Outputs
连接图
24-Pin DIP
24-Pin Quad Cerpak
DS100300-3
DS100300-2
© 1998 National Semiconductor Corporation
DS100300
www.national.com
